--DHcBFs7Z
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AMD announced a definitive agreement to acquire Toronto-based chip
startu=
p Taalas to expand its specialized AI inference
portfolio=C2=A0=E2=80= =8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0= =E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2= =A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C= =C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80= =8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0= =E2=80=8C=C2=A0=E2=80=8C=C2=A0=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80= =8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0= =E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2= =A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C= =C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80= =8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0
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=09=09TLDR=20
TLDR =
HARDWARE 2026-08-07
=F0=9F=93=B1=20
HEADLINES AND LAUNCHES
AM=
D TO BUY STARTUP TAALAS FOR NEW AI CHIPS (3 MINUTE READ) [4]=20
AMD ann=
ounced a definitive agreement to acquire Toronto-based chip
startup Taala=
s to expand its specialized AI inference portfolio.
Taalas develops custo=
m silicon architectures that hard-wire individual
AI model weights direct=
ly into semiconductor metal layers during
manufacturing. AMD plans to int=
egrate Taalas' low-cost,
ultra-efficient inference technology directly in=
to its broader
accelerator roadmap alongside Instinct GPUs.=20
ANTHRO=
PIC IS BUILDING AN IN-HOUSE CHIP TEAM FOR CLAUDE (3 MINUTE
READ) [5]=20
=
Anthropic has officially confirmed the assembly of an in-house chip
d=
esign team to engineer custom AI processors tailored for its Claude
platf=
orm. By co-designing hardware specifically alongside software
models, the=
AI startup aims to slash inference costs, boost execution
speeds, and op=
timize scaling for enterprise workloads.=20
=F0=9F=94=A8=20
ENGINEERI=
NG AND APPLICATIONS
BLUE ORIGIN TRACES MAY'S NEW GLENN EXPLOSION TO A=
FAULTY BE-4 ENGINE
VALVE (3 MINUTE READ) [6]=20
Blue Origin CEO Dave=
Limp said the May explosion that destroyed a New
Glenn rocket during a p=
relaunch engine test originated at the main
oxygen valve on one of its BE=
-4 engines, confirmed through hardware
recovery and inspection. The fix i=
s straightforward: small
modifications to the valve that can be quickly r=
etrofitted onto
existing engines, with the company aiming to return New G=
lenn to
flight later this year. The BE-4 also powers United Launch Allian=
ce's
Vulcan rocket, so ULA has been collaborating with Blue Origin on the=
investigation. The finding gives both companies a clear, containable
r=
oot cause rather than an open-ended engine redesign.=20
PCIE GEN 6 STOR=
AGE ARCHITECTURE SHOWCASED (3 MINUTES READ) [7]=20
Microchip Technology=
and Micron showcased a high-performance PCIe Gen
6 storage system demons=
tration at the Future of Memory and Storage
conference. Combining Microch=
ip's 3nm Switchtec PCIe 6.0 fanout
switches with Micron 9650 NVMe SSDs, t=
he architecture achieves
transfer speeds of 64 GT/s per lane=E2=80=94doub=
ling available bandwidth
over PCIe 5.0.=20
=F0=9F=A7=A0=20
RESEARCH=
AND PROTOTYPES
D-WAVE'S DUAL-RAIL QUBIT GATE HITS 99.9% FIDELITY, CU=
TTING
ERROR-CORRECTION OVERHEAD (4 MINUTE READ) [8]=20
D-Wave publish=
ed research in Nature demonstrating a new two-qubit
entangling gate for i=
ts superconducting "dual-rail" qubit
architecture, which is designed so t=
he most common quantum errors are
also the easiest kind to detect and fix=
. The gate hit roughly 99.9%
fidelity with fast ~500 nanosecond operation=
times, while preserving
native hardware-level error detection, meaning e=
rrors get caught
directly by the qubit design rather than requiring extra=
correction
circuitry bolted on afterward.=20
HOW TO SCALE AI ARITHME=
TIC EFFICIENTLY (4 MINUTE READ) [9]=20
This technical analysis explores=
how arithmetic specialization is
essential for scaling artificial intell=
igence compute performance. As
traditional transistor scaling slows down,=
hardware designers are
replacing general-purpose IEEE floating-point uni=
ts with specialized
arithmetic engines tailored to low-precision represen=
tations like FP8,
FP4, and Microscaling (MX) formats. By optimizing numbe=
r format
combinations and operation depth directly within silicon arithme=
tic
units, modern AI accelerators drastically reduce energy consumption=
per operation while maximizing throughput without swelling total die
a=
rea or power budgets.=20
=F0=9F=8E=81=20
MISCELLANEOUS
NVIDIA A=
ND GOOGLE ARE CROWDING TSMC'S N3 NODE, CREATING A RARE
OPENING FOR INTEL =
(5 MINUTE READ) [10]=20
Nvidia's next-gen Rubin GPUs are moving from 4n=
m to TSMC's 3nm node
just as Google's TPUs, which are already on N3, plan=
to stay there,
while new AI CPUs from Nvidia, Amazon, Microsoft, and Arm=
are
converging on the same process simultaneously. TSMC has already hit=
its planned N3 capacity and is still adding more, warning the node
cou=
ld stay "very tight" for years, with three of its four Arizona fabs
repor=
tedly already fully booked despite only one being operational,
driving re=
ported price hikes of up to 25% for some customers. That
squeeze creates =
a real opening for Intel, whose Fab 52 in Arizona just
entered full produ=
ction at 40,000 18A wafer starts per month, more
capacity than TSMC's ori=
ginal Fab 21 campus.=20
BREAKING THE MEMORY WALL WITH CXL (4 MINUTE REA=
D) [11]=20
The Diligence Stack analyzes how Compute Express Link (CXL)=
technology breaks the persistent memory wall in high-density AI
infras=
tructure. By utilizing PCIe physical interfaces to provide
memory-semanti=
c access, CXL enables memory expansion and multi-node
pooling directly ac=
ross server clusters. This architecture offloads
Key-Value caches and mas=
sive vector databases from constrained GPU
memory without severe latency =
penalties. Consequently, data centers
can eliminate stranded DRAM resourc=
es, drastically reducing hardware
costs, and scale memory capacity indepe=
ndently from fixed CPU channel
limits.=20
=E2=9A=A1=20
QUICK LINKS=
UNITREE EYES $7.4B VALUATION AHEAD OF SHANGHAI IPO (3 MINUTE READ)=
[12]=20
Chinese humanoid and quadruped robot maker Unitree is expect=
ed to be
valued at 50.6-55.9 billion yuan ($7.4-8.2 billion) after its pl=
anned
Shanghai IPO, a sharp jump from its 12 billion yuan valuation just=
last month, according to sponsor Citic Securities.=20
MOOVE RAISES $=
250 MILLION TO SCALE ROBOTAXI FLEET INFRASTRUCTURE (5
MINUTE READ) [13] =
Moove raised a Series C at a $2.1 billion valuation to build out
=
=E2=80=9CNests,=E2=80=9D robotics-first depots that charge, maintain, servi= ce, and
orchestrate autonomous vehicles continuously.=20
A REQUIEM FO=
R OPTANE: INTEL'S KV-CACHE KILLER THAT COULD HAVE EASED
THE RAM PRICE CRU=
NCH (4 MINUTE READ) [14]=20
Intel's discontinued Optane memory, which t=
hanks to its unmatched
write endurance and low latency for small random w=
rites, would have
been an ideal fit for today's write-intensive LLM KV-ca=
ching
workloads.=20
LUMILENS RAISES $700 MILLION TO REPLACE DATA-CENT=
ER WIRES WITH LIGHT
(3 MINUTE READ) [15]=20
Lumilens emerged from ste=
alth after securing over $700 million in
funding, reaching a $5.51 billio=
n valuation.=20
TSMC SITTING ON $1B WORTH OF APPLE A20 PRO SOCS DUE TO =
DRAM DEFICIT
(3 MINUTE READ) [16]=20
TSMC is reportedly holding nearl=
y $1 billion worth of Apple A20 Pro
processors in inventory that cannot s=
hip due to severe global mobile
DRAM shortages.=20
FRORE CLAIMS LIQUI=
DJET DROPS NVIDIA RUBIN GPU TEMPERATURES BY 10=C2=B0C
(3 MINUTE READ) [17=
]=20
Frore Systems claims its LiquidJet coldplate technology can lower=
Nvidia Rubin GPU junction temperatures by up to 12=C2=B0C, by etching
=
targeted microchannels near thermal hotspots.=20
WALDEN ROBOTICS SKIPS =
THE LEGS, BETTING WHEELS AND SIMPLE GRIPPERS
WIN IN FACTORIES (4 MINUTE R=
EAD) [18]=20
Walden Robotics, a Toyota Research Institute spinout, emer=
ged from
stealth with $300 million in funding at a $1.1 billion valuation=
.=20
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Thanks for read=
ing,=20
Kshitij Sudan [23] & Adi Nikumbh [24]=20
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[11]
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[13]
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[14]
https://www.theregister.com/storage/= 2026/07/29/a-requiem-for-optane-intels-kv-cache-killer-that-could-have-ease= d-the-ram-price-crunch/5280063?utm_source=3Dtldrhardware
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[17]
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<div style=3D"display: none; max-height: 0px; overflow: hidden;">AMD announ= ced a definitive agreement to acquire Toronto-based chip startup Taalas to = expand its specialized AI inference portfolio =E2=80=8C =E2=80=8C= =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C= =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C= =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C= =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C= =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2= =80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2= =80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2= =80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2= =80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2= =80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2=80=8C =E2= =80=8C </div>
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<div style=3D"text-align: center;">
<h1><strong>TLDR Hardware <span id=3D"date">2026-08-07</span></strong></h1> </div>
</td></tr></tbody></table>
<table style=3D"table-layout: fixed; width:100%;" width=3D"100%"><tbody></t= body></table>
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<div class=3D"text-block">
<div style=3D"text-align: center;"><span style=3D"font-size: 36px;">=F0=9F= =93=B1</span></div></div>
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<div class=3D"text-block">
<div style=3D"text-align: center;">
<h1><strong>Headlines and Launches</strong></h1>
</div>
</div>
</td></tr></tbody></table>
<table style=3D"table-layout: fixed; width: 100%;" width=3D"100%"><tbody><t= r><td style=3D"padding:0;border-collapse:collapse;border-spacing:0;margin:0=
;" valign=3D"top">
<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Fwww.unite.ai%2Famd-buys-taalas-to-put-hard-wired-ai-mod= els-in-its-accelerator-roadmap%2F%3Futm_source=3Dtldrhardware/1/0100019fdc5= d4964-54f7fca1-2db9-4f75-af71-1a858af3f1f9-000000/6YeauzcPGHPClpalWHxK82vW9= crifDuJSUUIPxMNqhE=3D452">
<span>
<strong>AMD to Buy Startup Taalas f=
or New AI Chips (3 minute read)</strong>
</span>
<span style=3D"font-family: "Helvetica Neue", Helvetica, Arial, V= erdana, sans-serif;">
AMD announced a definitive agreement to=
acquire Toronto-based chip startup Taalas to expand its specialized AI inf= erence portfolio. Taalas develops custom silicon architectures that hard-wi=
re individual AI model weights directly into semiconductor metal layers dur= ing manufacturing. AMD plans to integrate Taalas' low-cost, ultra-efficient=
inference technology directly into its broader accelerator roadmap alongsi=
de Instinct GPUs.
</span>
</span>
</div>
</td></tr></tbody></table>
<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Flinks.tldrnewsletter.com%2FZnXc7S/1/0100019fdc5d4964-54= f7fca1-2db9-4f75-af71-1a858af3f1f9-000000/gj1tuHShUiXYtuW2PtxCumzBuE9Zmsd6n= 1zSZSQ_CQY=3D452">
<span>
<strong>Anthropic Is Building an In= -House Chip Team for Claude (3 minute read)</strong>
</span>
<span style=3D"font-family: "Helvetica Neue", Helvetica, Arial, V= erdana, sans-serif;">
Anthropic has officially confirmed the = assembly of an in-house chip design team to engineer custom AI processors t= ailored for its Claude platform. By co-designing hardware specifically alon= gside software models, the AI startup aims to slash inference costs, boost = execution speeds, and optimize scaling for enterprise workloads.
</span>
</span>
</div>
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<div class=3D"text-block">
<div style=3D"text-align: center;"><span style=3D"font-size: 36px;">=F0=9F= =94=A8</span></div>
</div>
</td></tr></tbody></table>
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<div class=3D"text-block">
<div style=3D"text-align: center;">
<h1><strong>Engineering and Applications</strong></h1>
</div>
</div>
</td></tr></tbody></table>
<table style=3D"table-layout: fixed; width: 100%;" width=3D"100%"><tbody><t= r><td style=3D"padding:0;border-collapse:collapse;border-spacing:0;margin:0=
;" valign=3D"top">
<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Flinks.tldrnewsletter.com%2FAjKhh3/1/0100019fdc5d4964-54= f7fca1-2db9-4f75-af71-1a858af3f1f9-000000/Q1rD3jCaMZf7yBaiQEK1XOMdo0PAM4isN= c54wqVIo1k=3D452">
<span>
<strong>Blue Origin Traces May's Ne=
w Glenn Explosion to a Faulty BE-4 Engine Valve (3 minute read)</strong>
</span>
<span style=3D"font-family: "Helvetica Neue", Helvetica, Arial, V= erdana, sans-serif;">
Blue Origin CEO Dave Limp said the May = explosion that destroyed a New Glenn rocket during a prelaunch engine test = originated at the main oxygen valve on one of its BE-4 engines, confirmed t= hrough hardware recovery and inspection. The fix is straightforward: small = modifications to the valve that can be quickly retrofitted onto existing en= gines, with the company aiming to return New Glenn to flight later this yea=
r. The BE-4 also powers United Launch Alliance's Vulcan rocket, so ULA has = been collaborating with Blue Origin on the investigation. The finding gives=
both companies a clear, containable root cause rather than an open-ended e= ngine redesign.
</span>
</span>
</div>
</td></tr></tbody></table>
<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Fwww.thelec.net%2Fnews%2FarticleView.html%3Fidxno=3D1285= 9%26utm_source=3Dtldrhardware/1/0100019fdc5d4964-54f7fca1-2db9-4f75-af71-1a= 858af3f1f9-000000/v_65craIhijzfBXMpVQ6RK90L0wUD5DEdD-HphGPdz8=3D452">
<span>
<strong>PCIe Gen 6 Storage Architec= ture Showcased (3 minutes read)</strong>
</span>
<span style=3D"font-family: "Helvetica Neue", Helvetica, Arial, V= erdana, sans-serif;">
Microchip Technology and Micron showcas=
ed a high-performance PCIe Gen 6 storage system demonstration at the Future=
of Memory and Storage conference. Combining Microchip's 3nm Switchtec PCIe=
6.0 fanout switches with Micron 9650 NVMe SSDs, the architecture achieves = transfer speeds of 64 GT/s per lane=E2=80=94doubling available bandwidth ov=
er PCIe 5.0.
</span>
</span>
</div>
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<div class=3D"text-block">
<div style=3D"text-align: center;"><span style=3D"font-size: 36px;">=F0=9F= =A7=A0</span></div>
</div>
</td></tr></tbody></table>
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<div class=3D"text-block">
<div style=3D"text-align: center;">
<h1><strong>Research and Prototypes</strong></h1>
</div>
</div>
</td></tr></tbody></table>
<table style=3D"table-layout: fixed; width: 100%;" width=3D"100%"><tbody><t= r><td style=3D"padding:0;border-collapse:collapse;border-spacing:0;margin:0=
;" valign=3D"top">
<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Ffinance.yahoo.com%2Ftechnology%2Fai%2Farticles%2Fd-wave= -demonstrates-major-hardware-150500935.html%3Futm_source=3Dtldrhardware/1/0= 100019fdc5d4964-54f7fca1-2db9-4f75-af71-1a858af3f1f9-000000/gFIPf1SnNhfgFBp= TOG9vDm-JujhD4Ow-l90fyLiL4Js=3D452">
<span>
<strong>D-Wave's Dual-Rail Qubit Ga=
te Hits 99.9% Fidelity, Cutting Error-Correction Overhead (4 minute read)</= strong>
</span>
<span style=3D"font-family: "Helvetica Neue", Helvetica, Arial, V= erdana, sans-serif;">
D-Wave published research in Nature dem= onstrating a new two-qubit entangling gate for its superconducting "dual-ra= il" qubit architecture, which is designed so the most common quantum errors=
are also the easiest kind to detect and fix. The gate hit roughly 99.9% fi= delity with fast ~500 nanosecond operation times, while preserving native h= ardware-level error detection, meaning errors get caught directly by the qu= bit design rather than requiring extra correction circuitry bolted on after= ward.
</span>
</span>
</div>
</td></tr></tbody></table>
<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Fsemiengineering.com%2Fhow-to-scale-ai-arithmetic-effici= ently%2F%3Futm_source=3Dtldrhardware/1/0100019fdc5d4964-54f7fca1-2db9-4f75-= af71-1a858af3f1f9-000000/P85zG3H7KfAxEyS0KxpomtqlmMGOCD5JFtFFaogYFAc=3D452"=
<span>
<strong>How To Scale AI Arithmetic = Efficiently (4 minute read)</strong>
</span>
<span style=3D"font-family: "Helvetica Neue", Helvetica, Arial, V= erdana, sans-serif;">
This technical analysis explores how ar= ithmetic specialization is essential for scaling artificial intelligence co= mpute performance. As traditional transistor scaling slows down, hardware d= esigners are replacing general-purpose IEEE floating-point units with speci= alized arithmetic engines tailored to low-precision representations like FP=
8, FP4, and Microscaling (MX) formats. By optimizing number format combinat= ions and operation depth directly within silicon arithmetic units, modern A=
I accelerators drastically reduce energy consumption per operation while ma= ximizing throughput without swelling total die area or power budgets.
</span>
</span>
</div>
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<div class=3D"text-block">
<div style=3D"text-align: center;"><span style=3D"font-size: 36px;">=F0=9F= =8E=81</span></div></div>
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<div class=3D"text-block">
<div style=3D"text-align: center;"><strong><h1>Miscellaneous</h1></strong><= /div>
</div>
</td></tr></tbody></table>
<table bgcolor=3D"" style=3D"table-layout: fixed; width: 100%;" width=3D"10= 0%"><tbody><tr><td style=3D"padding:0;border-collapse:collapse;border-spaci= ng:0;margin:0;" valign=3D"top">
<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Fio-fund.com%2Fai-stocks%2Fnvidia-google-tsmc-n3-node-in= tel-opportunity%3Futm_source=3Dtldrhardware/1/0100019fdc5d4964-54f7fca1-2db= 9-4f75-af71-1a858af3f1f9-000000/hDJJAbmZITelaEz8_YRxqYIXTFmULAUuQcyvoUOxh8I= =3D452">
<span>
<strong>Nvidia and Google Are Crowd= ing TSMC's N3 Node, Creating a Rare Opening for Intel (5 minute read)</stro=
</span>
<span style=3D"font-family: "Helvetica Neue", Helvetica, Arial, V= erdana, sans-serif;">
Nvidia's next-gen Rubin GPUs are moving=
from 4nm to TSMC's 3nm node just as Google's TPUs, which are already on N3=
, plan to stay there, while new AI CPUs from Nvidia, Amazon, Microsoft, and=
Arm are converging on the same process simultaneously. TSMC has already hi=
t its planned N3 capacity and is still adding more, warning the node could = stay "very tight" for years, with three of its four Arizona fabs reportedly=
already fully booked despite only one being operational, driving reported = price hikes of up to 25% for some customers. That squeeze creates a real op= ening for Intel, whose Fab 52 in Arizona just entered full production at 40= ,000 18A wafer starts per month, more capacity than TSMC's original Fab 21 = campus.
</span>
</span>
</div>
</td></tr></tbody></table>
<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Fwww.thediligencestack.com%2Fp%2Fbreaking-the-memory-wal= l-with-cxl%3Futm_source=3Dtldrhardware/1/0100019fdc5d4964-54f7fca1-2db9-4f7= 5-af71-1a858af3f1f9-000000/RiVsev_c2Oxe6xe9hR5MZqt3kYH_5lPIop0R8VZyx84=3D45=
<span>
<strong>Breaking the Memory Wall Wi=
th CXL (4 minute read)</strong>
</span>
<span style=3D"font-family: "Helvetica Neue", Helvetica, Arial, V= erdana, sans-serif;">
The Diligence Stack analyzes how Comput=
e Express Link (CXL) technology breaks the persistent memory wall in high-d= ensity AI infrastructure. By utilizing PCIe physical interfaces to provide = memory-semantic access, CXL enables memory expansion and multi-node pooling=
directly across server clusters. This architecture offloads Key-Value cach=
es and massive vector databases from constrained GPU memory without severe = latency penalties. Consequently, data centers can eliminate stranded DRAM r= esources, drastically reducing hardware costs, and scale memory capacity in= dependently from fixed CPU channel limits.
</span>
</span>
</div>
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</td></tr></tbody></table>
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<div class=3D"text-block">
<div style=3D"text-align: center;"><span style=3D"font-size: 36px;">=E2=9A= =A1</span></div></div>
</td></tr></tbody></table>
<table align=3D"center" bgcolor=3D"" border=3D"0" cellpadding=3D"0" cellspa= cing=3D"0" width=3D"100%"><tbody><tr><td class=3D"container" style=3D"paddi= ng-top: 0px; padding-bottom: 0px;">
<div class=3D"text-block">
<div style=3D"text-align: center;">
<h1><strong>Quick Links</strong></h1>
</div>
</div>
</td></tr></tbody></table>
<table bgcolor=3D"" style=3D"table-layout: fixed; width: 100%;" width=3D"10= 0%"><tbody><tr><td style=3D"padding:0;border-collapse:collapse;border-spaci= ng:0;margin:0;" valign=3D"top">
<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Flinks.tldrnewsletter.com%2Fs4SmDc/1/0100019fdc5d4964-54= f7fca1-2db9-4f75-af71-1a858af3f1f9-000000/O5yWfR7LYGJozUSLG44ok_cHlHFW28p_2= Wkgo6d-RJE=3D452">
<span>
<strong>Unitree Eyes $7.4B Valuatio=
n Ahead of Shanghai IPO (3 minute read)</strong>
</span>
<span style=3D"font-family: "Helvetica Neue", Helvetica, Arial, V= erdana, sans-serif;">
Chinese humanoid and quadruped robot ma= ker Unitree is expected to be valued at 50.6-55.9 billion yuan ($7.4-8.2 bi= llion) after its planned Shanghai IPO, a sharp jump from its 12 billion yua=
n valuation just last month, according to sponsor Citic Securities.
</span>
</span>
</div>
</td></tr></tbody></table>
<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Fwww.moove.io%2Fdrive-to-own%2Fnews%2Fmoove-series-c%3Fu= tm_source=3Dtldrhardware/1/0100019fdc5d4964-54f7fca1-2db9-4f75-af71-1a858af= 3f1f9-000000/UtXo_T73F9rrlgWa5yejE9TKhNQUki2SJP14MvR-2Ss=3D452">
<span>
<strong>Moove raises $250 million t=
o scale robotaxi fleet infrastructure (5 minute read)</strong>
</span>
<span style=3D"font-family: "Helvetica Neue", Helvetica, Arial, V= erdana, sans-serif;">
Moove raised a Series C at a $2.1 billi=
on valuation to build out =E2=80=9CNests,=E2=80=9D robotics-first depots th=
at charge, maintain, service, and orchestrate autonomous vehicles continuou= sly.
</span>
</span>
</div>
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<table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=
<div class=3D"text-block">
<span>
<a href=3D"
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Intel's discontinued Optane memory, whi=
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Frore Systems claims its LiquidJet cold= plate technology can lower Nvidia Rubin GPU junction temperatures by up to = 12=C2=B0C, by etching targeted microchannels near thermal hotspots.
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Walden Robotics, a Toyota Research Inst= itute spinout, emerged from stealth with $300 million in funding at a $1.1 = billion valuation.
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