• Google launches Googlebook 💻, Intrinsic open-sources stack 🧠, Nvidia launches Isaac ROS 5.0 🤖

    From TLDR Hardware@VERT to All on Wed Sep 23 13:19:45 2026
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    Google has opened preorders for Googlebook, its new premium laptop
    catego=
    ry built on Android with ChromeOS-derived foundations under
    the=C2=A0= =E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2= =A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C= =C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80= =8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0= =E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2= =A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0= =E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2= =A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C= =C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80= =8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0= =E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=A0=E2=80=8C=C2=
    =A0


    Sign Up [1] |Advertise [2]|View Online [3]=20

    =09=09TLDR =


    TLDR HARDWARE 2026-09-23

    =F0=9F=93=B1=20

    HEADLINES AND LAUNCH=
    ES

    GOOGLEBOOK LAUNCHES FIVE ANDROID-BASED LAPTOPS OCTOBER 4, STARTING=
    AT
    $899 (4 MINUTE READ) [4]=20

    Google has opened preorders for Googl=
    ebook, its new premium laptop
    category built on Android with ChromeOS-der=
    ived foundations under the
    official OS name Googlebook OS, five launch mo=
    dels from Acer, ASUS,
    Dell, HP, and Lenovo priced at $899-$1,299, hitting=
    US shelves October
    4. The lineup runs on Intel Core Ultra Series 3 or Sn=
    apdragon X Elite
    chips with 40+ TOPS NPUs (MediaTek-powered models to fol=
    low later), a
    16GB RAM baseline with 32GB options, touchscreens up to 2.8=
    K, and
    bodies built from aluminum, magnesium, or carbon fiber.=20

    ALP=
    HABET'S INTRINSIC OPEN-SOURCES CORE ROBOTICS STACK, SHIPS A
    MACHINE-TENDI=
    NG REFERENCE DESIGN (4 MINUTE READ) [5]=20

    At ROSCon 2026 in Toronto, A=
    lphabet's Intrinsic released Intrinsic
    Core, an Apache 2.0-licensed, ROS-=
    compatible set of robotics
    capabilities pulled directly from the same pla=
    tform Intrinsic uses for
    real manufacturing deployments, aiming to lower =
    the barrier for
    developers building industrial robotics applications. The=
    package
    includes a hardware-agnostic real-time control framework that le=
    ts
    robots dynamically adapt mid-trajectory to sensor input, 6-DoF pose
    =
    estimation built on NVIDIA FoundationPose for handling parts without
    rigi=
    d physical fixtures, automatic motion and grasp planning,
    Gazebo-powered =
    simulation, camera calibration, and pre-tuned ROS
    drivers for supported r=
    obots, grippers, and 3D cameras.=20

    =F0=9F=94=A8=20

    ENGINEERING AND A=
    PPLICATIONS

    META ANNOUNCES PETAL, THE FIRST PETABIT-CAPACITY TRANSOCE=
    ANIC SUBSEA
    CABLE, USING 2-CORE FIBER (5 MINUTE READ) [6]=20

    Meta's P=
    etal cable will span roughly 7,000km between France and the
    US, carrying =
    1 petabit per second, double the capacity of any subsea
    cable at transatl=
    antic distance, becoming the first system to deploy
    multi-core fiber at s=
    cale. Since the 2010s, coherent optical
    transmission pushed fiber capacit=
    y 10x before hitting the Shannon
    Limit, forcing the industry toward spati=
    al division multiplexing,
    adding more fiber pairs to a cable, which Meta =
    scaled from 8 pairs on
    Marea to 24 on Anjana. Rather than pushing to 48 f=
    iber pairs or
    widening the optical band, Petal packs 2-core fiber into a =
    24-pair
    system, physically equivalent to 48 pairs but using ultra-pure
    =
    synthetic silica and carefully controlled refractive-index differences
    be=
    tween the cores to keep crosstalk nearly immeasurable.=20

    CXMT CLAIMS F=
    IFTH-GEN DRAM PLATFORM MATCHES INDUSTRY'S MOST ADVANCED
    NODES (3 MINUTE R=
    EAD) [7]=20

    CXMT said its fifth-generation DRAM platform has entered ma=
    ss
    production, claiming process capability "on par with the most advanced=

    mass-produced nodes out there in the industry." The company reduced
    th=
    e spacing of key data-storage structures to 11.95 nanometers using
    "quadr=
    uple patterning," a technique that repeats manufacturing steps
    to produce=
    finer circuit patterns without needing EUV lithography, and
    says the new=
    platform yields at least 50% more dies per wafer than its
    fourth generat=
    ion on an 8-gigabit baseline.=20

    =F0=9F=A7=A0=20

    RESEARCH AND PROTOTY=
    PES

    NVIDIA ISAAC ROS 5.0 BRINGS AI AGENTS INTO ROBOTICS DEVELOPMENT,=

    SPANS JETSON ORIN NANO TO JETSON THOR (5 MINUTE READ) [8]=20

    NVIDIA =
    released Isaac ROS 5.0 at ROSCon in Toronto, adding support
    for ROS Lyric=
    al and Ubuntu 24.04 and contributing a vendor-neutral
    accelerated memory =
    transport interface to ROS Lyrical alongside the
    Open Source Robotics All=
    iance, giving the broader 1.3-million-user ROS
    community a standard way t=
    o move data efficiently across different
    compute hardware, including GPUs=
    .=20

    AI AGENTS DESIGN CHIPS 2.6X FASTER BY WORKING IN HIGH-LEVEL HLS
    =
    BEFORE DROPPING TO RTL (3 MINUTE READ) [9]=20

    Most LLM chip-design agen=
    ts work directly at RTL, the low-level
    hardware description that specifie=
    s exact circuit behavior, which
    forces the agent to grapple with fine-gra=
    ined optimization details
    from the very start. This paper tests whether l=
    etting agents design at
    a higher abstraction level first, High-Level Synt=
    hesis (HLS), which
    compiles from something closer to software code down i=
    nto RTL,
    produces better results, comparing four workflows including a co=
    mbined
    approach called Agent-based HLS with RTL Refinement (AHRR): the ag=
    ent
    designs in HLS, then a separate refinement pass drops down to RTL to=

    recover optimizations the higher-level abstraction misses.=20

    =
    =F0=9F=8E=81=20

    MISCELLANEOUS

    MEDIATEK DEBUTS DIMENSITY CX C10 MAX=
    , A 3NM SOC FOR AI-FIRST
    "GOOGLEBOOK" LAPTOPS (3 MINUTE READ) [10]=20

    =
    MediaTek has unveiled the Dimensity CX C10 Max, the first chip in its
    ne=
    w Dimensity Compute Experiences family, built on TSMC's 3nm process
    with =
    an all-big-core octa-core CPU, an 11-core GPU, and MediaTek's
    8th-gen NPU=
    . The company claims up to 15% faster multi-thread
    performance and up to =
    50% less single-thread power draw than
    alternative platforms, enough effi=
    ciency headroom to enable fanless,
    ultra-thin laptop designs with up to 1=
    9 hours of battery life.=20

    SAUDI ARABIA'S CEER UNVEILS EXOBOT EVS, BUI=
    LT WITH BMW AND FOXCONN
    BACKING (4 MINUTE READ) [11]=20

    Ceer, Saudi A=
    rabia's first homegrown EV brand, unveiled the Exobot
    sedan and SUV, the =
    opening two of a planned seven-vehicle lineup, at
    its manufacturing compl=
    ex in King Abdullah Economic City. The company
    is a joint venture between=
    Saudi Arabia's Public Investment Fund and
    Foxconn, leveraging BMW licens=
    ing for the underlying platform along
    with partnerships spanning Hyundai =
    Transys and Rimac, and both
    Tron-esque, gullwing-doored models were built=
    with design input
    personally pushed by Crown Prince Mohammed bin Salman.=
    =20

    =E2=9A=A1=20

    QUICK LINKS

    APPLE SEEKS DIRECT ACCESS TO OPENA=
    I'S HARDWARE R&D RECORDS IN TRADE
    SECRETS CASE (4 MINUTE READ) [12]=20
    =

    In a joint court filing, Apple asked to let its own forensic experts
    =
    directly examine the digital images OpenAI's experts used to analyze
    form=
    er Apple engineer Chang Liu's devices, arguing its expert already
    found "=
    critical flaws" and incorrect conclusions drawn from zero-byte
    files and =
    empty metadata fields.=20

    QUALCOMM'S SNAPDRAGON 8 ELITE EXTREME GEN 6 R=
    UNS A 30B-PARAMETER MOE
    MODEL LOCALLY ON PHONES (3 MINUTE READ) [13]=20
    =

    Qualcomm unveiled its Snapdragon 8 Elite Gen 6 and Elite Extreme Gen
    =
    6 at its annual Snapdragon Summit, both built with a new dedicated
    sensin=
    g hub capable of running small models up to 200 million
    parameters locall=
    y.=20

    NVIDIA LAUNCHES DSX READY, A QUALIFICATION PROGRAM FOR AI FACTORY=

    POWER AND COOLING HARDWARE (3 MINUTE READ) [14]=20

    DSX Ready is a pr=
    ogram that qualifies partner power and cooling
    products against its DSX A=
    I factory reference design requirements,
    starting with battery energy sto=
    rage systems and cooling distribution
    units.=20

    UNITREE LAUNCHES DEX5=
    -S, A 22-DOF HUMAN-SIZED DEXTEROUS HAND STARTING
    AT $6,500 (3 MINUTE READ=
    ) [15]=20

    Unitree's Dex5-S is a five-finger robotic hand scaled to matc=
    h human
    hand size, with every one of its 22 degrees of freedom motor-driv=
    en
    and backdrivable via dual-encoder control.=20

    COGNEX ACQUIRES REAL=
    SENSE FOR $500M TO EXPAND ROBOTIC VISION PLATFORM
    (4 MINUTE READ) [16] =


    Cognex is buying RealSense, a depth-sensing camera and vision
    tech=
    nology business Intel spun out in 2025, for $500 million cash.=20

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    o advertise in TLDR? =F0=9F=93=B0

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    hitij Sudan [21] & Adi Nikumbh [22]=20

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    re
    [11] https://arstechnica.com/cars/2026/09/saudi-arabia-wants-a-car-ind= ustry-launches-ceer-with-two-evs/?utm_source=3Dtldrhardware
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    [13] = https://techcrunch.com/2026/09/22/qualcomm-launches-two-new-smartphone-chip= s-with-emphasis-on-ai/?utm_source=3Dtldrhardware
    [14] https://blogs.nvidi= a.com/blog/dsx-ready-ai-factories-power-cooling/?utm_source=3Dtldrhardware=

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    <div style=3D"display: none; max-height: 0px; overflow: hidden;">Google has=
    opened preorders for Googlebook, its new premium laptop category built on = Android with ChromeOS-derived foundations under the&nbsp;=E2=80=8C&nbsp;=E2= =80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2= =80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2= =80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2= =80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2= =80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;&nb= sp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nb= sp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nb= sp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nb= sp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nb= sp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nbsp;=E2=80=8C&nb= sp;=E2=80=8C&nbsp;</div>

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    <div style=3D"text-align: center;">

    <h1><strong>TLDR Hardware <span id=3D"date">2026-09-23</span></strong></h1> </div>
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    <table style=3D"table-layout: fixed; width:100%;" width=3D"100%"><tbody></t= body></table>
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    <div class=3D"text-block">
    <div style=3D"text-align: center;"><span style=3D"font-size: 36px;">=F0=9F= =93=B1</span></div></div>
    </td></tr></tbody></table>

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    <h1><strong>Headlines and Launches</strong></h1>
    </div>
    </div>
    </td></tr></tbody></table>

    <table style=3D"table-layout: fixed; width: 100%;" width=3D"100%"><tbody><t= r><td style=3D"padding:0;border-collapse:collapse;border-spacing:0;margin:0=
    ;" valign=3D"top">

    <table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=

    <div class=3D"text-block">
    <span>
    <a href=3D"https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Farstechnica.com%2Fgadgets%2F2026%2F09%2Fgooglebook-lapt= ops-launch-october-4-starting-at-899-preorders-for-five-models-live-today%2= F%3Futm_source=3Dtldrhardware/1/010001a0ce6c1715-d1561d11-0a6a-4285-9698-87= 7792249c51-000000/5kONjqv7CtkRhspQgX5YwebelhC1DgqJBkGMJkp6G0A=3D452">
    <span>
    <strong>Googlebook launches five An= droid-based laptops October 4, starting at $899 (4 minute read)</strong>
    </span>



    <span style=3D"font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, V= erdana, sans-serif;">
    Google has opened preorders for Googleb= ook, its new premium laptop category built on Android with ChromeOS-derived=
    foundations under the official OS name Googlebook OS, five launch models f= rom Acer, ASUS, Dell, HP, and Lenovo priced at $899-$1,299, hitting US shel= ves October 4. The lineup runs on Intel Core Ultra Series 3 or Snapdragon X=
    Elite chips with 40+ TOPS NPUs (MediaTek-powered models to follow later), =
    a 16GB RAM baseline with 32GB options, touchscreens up to 2.8K, and bodies = built from aluminum, magnesium, or carbon fiber.
    </span>
    </span>
    </div>
    </td></tr></tbody></table>

    <table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=

    <div class=3D"text-block">
    <span>
    <a href=3D"https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Fwww.intrinsic.ai%2Fblog%2Fposts%2Fintroducing-intrinsic= -core%3Futm_source=3Dtldrhardware/1/010001a0ce6c1715-d1561d11-0a6a-4285-969= 8-877792249c51-000000/Lye_Lp5Bil15Bgh_TIPmC3fVOt8Z_zNAHdEpbjplGGs=3D452">
    <span>
    <strong>Alphabet's Intrinsic Open-S= ources Core Robotics Stack, Ships a Machine-Tending Reference Design (4 min= ute read)</strong>
    </span>



    <span style=3D"font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, V= erdana, sans-serif;">
    At ROSCon 2026 in Toronto, Alphabet's I= ntrinsic released Intrinsic Core, an Apache 2.0-licensed, ROS-compatible se=
    t of robotics capabilities pulled directly from the same platform Intrinsic=
    uses for real manufacturing deployments, aiming to lower the barrier for d= evelopers building industrial robotics applications. The package includes a=
    hardware-agnostic real-time control framework that lets robots dynamically=
    adapt mid-trajectory to sensor input, 6-DoF pose estimation built on NVIDI=
    A FoundationPose for handling parts without rigid physical fixtures, automa= tic motion and grasp planning, Gazebo-powered simulation, camera calibratio=
    n, and pre-tuned ROS drivers for supported robots, grippers, and 3D cameras=
    .
    </span>
    </span>
    </div>
    </td></tr></tbody></table>

    </td></tr></tbody></table>

    <table align=3D"center" bgcolor=3D"" border=3D"0" cellpadding=3D"0" cellspa= cing=3D"0" width=3D"100%"><tbody><tr><td class=3D"container" style=3D"paddi= ng-top: 0px; padding-bottom: 0px;">
    <div class=3D"text-block">
    <div style=3D"text-align: center;"><span style=3D"font-size: 36px;">=F0=9F= =94=A8</span></div>
    </div>
    </td></tr></tbody></table>

    <table align=3D"center" bgcolor=3D"" border=3D"0" cellpadding=3D"0" cellspa= cing=3D"0" width=3D"100%"><tbody><tr><td class=3D"container" style=3D"paddi= ng-top: 0px; padding-bottom: 0px;">
    <div class=3D"text-block">
    <div style=3D"text-align: center;">

    <h1><strong>Engineering and Applications</strong></h1>
    </div>
    </div>
    </td></tr></tbody></table>


    <table style=3D"table-layout: fixed; width: 100%;" width=3D"100%"><tbody><t= r><td style=3D"padding:0;border-collapse:collapse;border-spacing:0;margin:0=
    ;" valign=3D"top">

    <table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=

    <div class=3D"text-block">
    <span>
    <a href=3D"https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Fengineering.fb.com%2F2026%2F09%2F21%2Fconnectivity%2Fpe= tal-petabit-transoceanic-subsea-cable%2F%3Futm_source=3Dtldrhardware/1/0100= 01a0ce6c1715-d1561d11-0a6a-4285-9698-877792249c51-000000/AyUSfMvj9vBbNcClKu= r8f8YNJFY0ONRAUWYvR2W74kE=3D452">
    <span>
    <strong>Meta announces Petal, the f= irst petabit-capacity transoceanic subsea cable, using 2-core fiber (5 minu=
    te read)</strong>
    </span>



    <span style=3D"font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, V= erdana, sans-serif;">
    Meta's Petal cable will span roughly 7,= 000km between France and the US, carrying 1 petabit per second, double the = capacity of any subsea cable at transatlantic distance, becoming the first = system to deploy multi-core fiber at scale. Since the 2010s, coherent optic=
    al transmission pushed fiber capacity 10x before hitting the Shannon Limit,=
    forcing the industry toward spatial division multiplexing, adding more fib=
    er pairs to a cable, which Meta scaled from 8 pairs on Marea to 24 on Anjan=
    a. Rather than pushing to 48 fiber pairs or widening the optical band, Peta=
    l packs 2-core fiber into a 24-pair system, physically equivalent to 48 pai=
    rs but using ultra-pure synthetic silica and carefully controlled refractiv= e-index differences between the cores to keep crosstalk nearly immeasurable=
    .
    </span>
    </span>
    </div>
    </td></tr></tbody></table>

    <table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=

    <div class=3D"text-block">
    <span>
    <a href=3D"https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Flinks.tldrnewsletter.com%2FPLDHJS/1/010001a0ce6c1715-d1= 561d11-0a6a-4285-9698-877792249c51-000000/aMBm86Qs18olL23EjDADf7hobvw7C4D3I= jHf9HO9HU8=3D452">
    <span>
    <strong>CXMT claims fifth-gen DRAM = platform matches industry's most advanced nodes (3 minute read)</strong>
    </span>



    <span style=3D"font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, V= erdana, sans-serif;">
    CXMT said its fifth-generation DRAM pla= tform has entered mass production, claiming process capability "on par with=
    the most advanced mass-produced nodes out there in the industry." The comp= any reduced the spacing of key data-storage structures to 11.95 nanometers = using "quadruple patterning," a technique that repeats manufacturing steps =
    to produce finer circuit patterns without needing EUV lithography, and says=
    the new platform yields at least 50% more dies per wafer than its fourth g= eneration on an 8-gigabit baseline.
    </span>
    </span>
    </div>
    </td></tr></tbody></table>

    </td></tr></tbody></table>

    <table align=3D"center" bgcolor=3D"" border=3D"0" cellpadding=3D"0" cellspa= cing=3D"0" width=3D"100%"><tbody><tr><td class=3D"container" style=3D"paddi= ng-top: 0px; padding-bottom: 0px;">
    <div class=3D"text-block">
    <div style=3D"text-align: center;"><span style=3D"font-size: 36px;">=F0=9F= =A7=A0</span></div>
    </div>
    </td></tr></tbody></table>

    <table align=3D"center" bgcolor=3D"" border=3D"0" cellpadding=3D"0" cellspa= cing=3D"0" width=3D"100%"><tbody><tr><td class=3D"container" style=3D"paddi= ng-top: 0px; padding-bottom: 0px;">
    <div class=3D"text-block">
    <div style=3D"text-align: center;">

    <h1><strong>Research and Prototypes</strong></h1>
    </div>
    </div>
    </td></tr></tbody></table>

    <table style=3D"table-layout: fixed; width: 100%;" width=3D"100%"><tbody><t= r><td style=3D"padding:0;border-collapse:collapse;border-spacing:0;margin:0=
    ;" valign=3D"top">

    <table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=

    <div class=3D"text-block">
    <span>
    <a href=3D"https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Fblogs.nvidia.com%2Fblog%2Fisaac-ros-5-0-agentic-open-so= urce-robotics%2F%3Futm_source=3Dtldrhardware/1/010001a0ce6c1715-d1561d11-0a= 6a-4285-9698-877792249c51-000000/6Pyh5YCSSGCSjz--ave_CMZvVok62LIVW2VNxFq3OX= Y=3D452">
    <span>
    <strong>NVIDIA Isaac ROS 5.0 brings=
    AI agents into robotics development, spans Jetson Orin Nano to Jetson Thor=
    (5 minute read)</strong>
    </span>



    <span style=3D"font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, V= erdana, sans-serif;">
    NVIDIA released Isaac ROS 5.0 at ROSCon=
    in Toronto, adding support for ROS Lyrical and Ubuntu 24.04 and contributi=
    ng a vendor-neutral accelerated memory transport interface to ROS Lyrical a= longside the Open Source Robotics Alliance, giving the broader 1.3-million-= user ROS community a standard way to move data efficiently across different=
    compute hardware, including GPUs.
    </span>
    </span>
    </div>
    </td></tr></tbody></table>

    <table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=

    <div class=3D"text-block">
    <span>
    <a href=3D"https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Farxiv.org%2Fabs%2F2609.21157%3Futm_source=3Dtldrhardwar= e/1/010001a0ce6c1715-d1561d11-0a6a-4285-9698-877792249c51-000000/ArotRWX7Ve= AcP-VJvR7YLOSGEx1RKVHt98zJf8TldAU=3D452">
    <span>
    <strong>AI agents design chips 2.6x=
    faster by working in high-level HLS before dropping to RTL (3 minute read)= </strong>
    </span>



    <span style=3D"font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, V= erdana, sans-serif;">
    Most LLM chip-design agents work direct=
    ly at RTL, the low-level hardware description that specifies exact circuit = behavior, which forces the agent to grapple with fine-grained optimization = details from the very start. This paper tests whether letting agents design=
    at a higher abstraction level first, High-Level Synthesis (HLS), which com= piles from something closer to software code down into RTL, produces better=
    results, comparing four workflows including a combined approach called Age= nt-based HLS with RTL Refinement (AHRR): the agent designs in HLS, then a s= eparate refinement pass drops down to RTL to recover optimizations the high= er-level abstraction misses.
    </span>
    </span>
    </div>
    </td></tr></tbody></table>

    </td></tr></tbody></table>

    <table align=3D"center" bgcolor=3D"" border=3D"0" cellpadding=3D"0" cellspa= cing=3D"0" width=3D"100%"><tbody><tr><td class=3D"container" style=3D"paddi= ng-top: 0px; padding-bottom: 0px;">
    <div class=3D"text-block">
    <div style=3D"text-align: center;"><span style=3D"font-size: 36px;">=F0=9F= =8E=81</span></div></div>
    </td></tr></tbody></table>

    <table align=3D"center" bgcolor=3D"" border=3D"0" cellpadding=3D"0" cellspa= cing=3D"0" width=3D"100%"><tbody><tr><td class=3D"container" style=3D"paddi= ng-top: 0px; padding-bottom: 0px;">
    <div class=3D"text-block">
    <div style=3D"text-align: center;"><strong><h1>Miscellaneous</h1></strong><= /div>
    </div>
    </td></tr></tbody></table>

    <table bgcolor=3D"" style=3D"table-layout: fixed; width: 100%;" width=3D"10= 0%"><tbody><tr><td style=3D"padding:0;border-collapse:collapse;border-spaci= ng:0;margin:0;" valign=3D"top">

    <table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=

    <div class=3D"text-block">
    <span>
    <a href=3D"https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Fwww.embedded.com%2Fmediatek-debuts-cx-c10-soc-for-ai-fi= rst-googlebook-laptops%3Futm_source=3Dtldrhardware/1/010001a0ce6c1715-d1561= d11-0a6a-4285-9698-877792249c51-000000/nkS_k7Vd85atadOlkuZn0a4jPBjzbsAtl_6h= kf1xLyw=3D452">
    <span>
    <strong>MediaTek debuts Dimensity C=
    X C10 Max, a 3nm SoC for AI-first "Googlebook" laptops (3 minute read)</str=

    </span>



    <span style=3D"font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, V= erdana, sans-serif;">
    MediaTek has unveiled the Dimensity CX = C10 Max, the first chip in its new Dimensity Compute Experiences family, bu= ilt on TSMC's 3nm process with an all-big-core octa-core CPU, an 11-core GP=
    U, and MediaTek's 8th-gen NPU. The company claims up to 15% faster multi-th= read performance and up to 50% less single-thread power draw than alternati=
    ve platforms, enough efficiency headroom to enable fanless, ultra-thin lapt=
    op designs with up to 19 hours of battery life.
    </span>
    </span>
    </div>
    </td></tr></tbody></table>

    <table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=

    <div class=3D"text-block">
    <span>
    <a href=3D"https://tracking.tldrnewsletter.= com/CL0/https:%2F%2Farstechnica.com%2Fcars%2F2026%2F09%2Fsaudi-arabia-wants= -a-car-industry-launches-ceer-with-two-evs%2F%3Futm_source=3Dtldrhardware/1= /010001a0ce6c1715-d1561d11-0a6a-4285-9698-877792249c51-000000/_QTDaEaW1S89c= j67jTO6jjbOMJFXuJuT8Qsdyxqisgw=3D452">
    <span>
    <strong>Saudi Arabia's Ceer unveils=
    Exobot EVs, built with BMW and Foxconn backing (4 minute read)</strong>
    </span>



    <span style=3D"font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, V= erdana, sans-serif;">
    Ceer, Saudi Arabia's first homegrown EV=
    brand, unveiled the Exobot sedan and SUV, the opening two of a planned sev= en-vehicle lineup, at its manufacturing complex in King Abdullah Economic C= ity. The company is a joint venture between Saudi Arabia's Public Investmen=
    t Fund and Foxconn, leveraging BMW licensing for the underlying platform al= ong with partnerships spanning Hyundai Transys and Rimac, and both Tron-esq= ue, gullwing-doored models were built with design input personally pushed b=
    y Crown Prince Mohammed bin Salman.
    </span>
    </span>
    </div>
    </td></tr></tbody></table>

    </td></tr></tbody></table>



    <table align=3D"center" bgcolor=3D"" border=3D"0" cellpadding=3D"0" cellspa= cing=3D"0" width=3D"100%"><tbody><tr><td class=3D"container" style=3D"paddi= ng-top: 0px; padding-bottom: 0px;">
    <div class=3D"text-block">
    <div style=3D"text-align: center;"><span style=3D"font-size: 36px;">=E2=9A= =A1</span></div></div>
    </td></tr></tbody></table>

    <table align=3D"center" bgcolor=3D"" border=3D"0" cellpadding=3D"0" cellspa= cing=3D"0" width=3D"100%"><tbody><tr><td class=3D"container" style=3D"paddi= ng-top: 0px; padding-bottom: 0px;">
    <div class=3D"text-block">
    <div style=3D"text-align: center;">

    <h1><strong>Quick Links</strong></h1>
    </div>
    </div>
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    <table bgcolor=3D"" style=3D"table-layout: fixed; width: 100%;" width=3D"10= 0%"><tbody><tr><td style=3D"padding:0;border-collapse:collapse;border-spaci= ng:0;margin:0;" valign=3D"top">

    <table align=3D"center" border=3D"0" cellpadding=3D"0" cellspacing=3D"0" wi= dth=3D"100%"><tbody><tr><td class=3D"container" style=3D"padding: 15px 15px=

    <div class=3D"text-block">
    <span>
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    </span>



    <span style=3D"font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, V= erdana, sans-serif;">
    In a joint court filing, Apple asked to=
    let its own forensic experts directly examine the digital images OpenAI's = experts used to analyze former Apple engineer Chang Liu's devices, arguing = its expert already found "critical flaws" and incorrect conclusions drawn f= rom zero-byte files and empty metadata fields.
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    <span style=3D"font-family: &quot;Helvetica Neue&quot;, Helvetica, Arial, V= erdana, sans-serif;">
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